WDC 65C265

The Western Design Center (WDC) W65C265S is a 16-bit microcontroller intended for low-power and high reliability roles. It is a member of the MOS 6502 family, based on the CMOS WDC 65C816 CPU.

The W65C265S consists of a W65C816S (static) CPU, 8 KB of Read Only Memory (ROM), 576 bytes of Random Access Memory (RAM), a processor cache under software control, eight 16-bit timers with maskable interrupts, an interrupt-driven parallel bus (PIB), four universal asynchronous receiver-transmitters (UARTs), a watchdog timer that fires a restart interrupt, twenty-nine priority encoded interrupts, a time-of-day clock, two sound generators, a bus control register (BCR) for external memory bus control, interface circuitry for peripheral devices, ABORT input for low cost virtual memory interface, and many low power features.

Hi-Rel low power CMOS process
Operating ambient temperature = 0 °C to +70 °C
Single 2.8 V to 5.5 V power supply
Static to 8 MHz clock operation
W65C816S compatible CPU
16 MB linear address space
Twenty-nine priority encoded interrupts
Four UARTS's
Time of Day (ToD) clock features
8 x 16 bit timer/counters
Bus Control Register
Many bus operating features and modes
8 Programmable chip select outputs
Low cost surface mount 84 and 100 lead packages
Macro and Cross assemblers available
C compilers available
Automatically shifts speed for slow memory or peripherals