India Launches DHRUV64: A Milestone in Indigenous Semiconductor Technology
A Step Towards Aatmanirbhar Bharat in Chip Design
In a significant boost to India's semiconductor self-reliance, the Centre for Development of Advanced Computing (C-DAC) has unveiled DHRUV64, the country's first indigenously designed 1.0 GHz, 64-bit dual-core microprocessor. Also known as the VEGA AS2161, this processor marks a pivotal achievement under the Microprocessor Development Programme (MDP) and the Digital India RISC-V (DIR-V) initiative.
The DHRUV64 chip, featuring clear markings like "DIR-V VEGA", "DHRUV64", "AS2161", and "CDAC".
Key Features of DHRUV64
DHRUV64 is built on the open-source RISC-V instruction set architecture (ISA), which allows royalty-free innovation and reduces dependency on proprietary technologies.
- Architecture: 64-bit dual-core, 16-stage pipelined, superscalar out-of-order execution
- Clock Speed: 1.0 GHz
- Design Highlights: Enhanced efficiency, superior multitasking, improved reliability, and seamless integration with external hardware
- Capabilities: Supports Linux operating system, making it suitable for complex applications
- Fabrication: Utilizes modern process technologies (likely around 28nm, based on India's current roadmap)
This processor represents a leap from previous indigenous efforts like THEJAS32 and THEJAS64, being the third fabricated chip under the DIR-V program.
Close-up view of the DHRUV64 processor package.
Applications and Strategic Importance
DHRUV64 is versatile and targeted at both strategic and commercial sectors:
- 5G telecommunications infrastructure
- Automotive electronics
- Consumer devices
- Industrial automation and control systems
- Internet of Things (IoT) devices
- Defense and critical national infrastructure
India consumes approximately 20% of the world's microprocessors but has historically relied heavily on imports. This dependence poses risks to supply chain security and national sovereignty, especially in sensitive areas. DHRUV64 addresses these concerns by providing a trusted, homegrown alternative that enhances security and reduces vulnerability to global disruptions.
As part of the broader VEGA processor family, DHRUV64 paves the way for future advancements, including quad-core variants like DHANUSH64 and higher-performance models targeting even octa-core and beyond.
Another perspective of the indigenous DHRUV64 microprocessor.
Why This Matters for India's Tech Ecosystem
The adoption of RISC-V – an open and free ISA – empowers Indian startups, researchers, and companies to innovate without expensive licensing fees associated with architectures like ARM or x86. Combined with government initiatives, this fosters a vibrant domestic ecosystem for electronics system design and manufacturing (ESDM).
While the 1 GHz clock speed and dual-core setup may seem modest compared to flagship consumer chips, DHRUV64 prioritizes reliability, efficiency, and security for embedded and edge applications where stability is paramount.
This launch underscores steady progress in India's semiconductor journey, building on projects like SHAKTI (IIT Madras), AJIT (IIT Bombay), and VIKRAM (ISRO). It's not just about one chip – it's about creating a foundation for future generations of high-performance, multi-core processors that could power everything from smart cities to advanced defense systems.
Looking Ahead
C-DAC is already developing next-generation processors in the VEGA series, including quad-core DHANUSH64 (expected at higher clocks) and more advanced variants. With plans for domestic fabrication facilities coming online soon, India is positioning itself as a potential global player in RISC-V-based computing.
DHRUV64 is more than a microprocessor – it's a symbol of technological sovereignty and a catalyst for innovation in the world's largest democracy.
What are your thoughts on India's push for indigenous chips? Will RISC-V help bridge the gap with global leaders? Share in the comments!
Tags: #IndiaTech #Semiconductors #DHRUV64 #RISC-V #AatmanirbharBharat #CDAC #VEGAProcessor #TechNews
Source: Based on official announcements and reports from December 2025.