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RE: Stacked FET, a 3D architecture that stacks transistors vertically/Stacked FET, una arquitectura 3D que apila transistores verticalmente
Instead of placing them side-by-side as done previously in a normal layout, Samsung's latest 3D Stacked FET architecture stacks up all of the transistors in the vertical direction (up) thus increasing chip density and improving overall chip efficiency without any additional reductions in component size.
This new technology will enable the development of faster and far more energy-efficient AI/computing processors and ultimately help continue to push technological advancement beyond the traditional boundaries of Moore's Law.